The Resource High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings, Per Stenström [and others] (eds.)

High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings, Per Stenström [and others] (eds.)

Label
High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings
Title
High performance embedded architectures and compilers
Title remainder
third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings
Statement of responsibility
Per Stenström [and others] (eds.)
Title variation
HiPEAC 2008
Creator
Contributor
Subject
Genre
Language
eng
Member of
Cataloging source
GW5XE
Dewey number
004.2/2
Illustrations
illustrations
Index
index present
LC call number
TK7895.E42
LC item number
H57 2008eb
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
Series statement
  • LNCS sublibrary. SL 1, Theoretical computer science and general issues
  • Lecture notes in computer science,
Series volume
4917
Label
High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings, Per Stenström [and others] (eds.)
Publication
Bibliography note
Includes bibliographical references and index
http://library.link/vocab/branchCode
  • net
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable -- ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache
Control code
ocn233973811
Dimensions
unknown
Extent
1 online resource (xiii, 400 pages)
Form of item
online
Isbn
9783540775607
Lccn
2007942570
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-540-77560-7
Other physical details
illustrations
http://library.link/vocab/ext/overdrive/overdriveId
978-3-540-77559-1
http://library.link/vocab/recordID
.b23243259
Specific material designation
remote
System control number
  • (OCoLC)233973811
  • sks3540775595

Library Locations

    • Deakin University Library - Geelong Waurn Ponds CampusBorrow it
      75 Pigdons Road, Waurn Ponds, Victoria, 3216, AU
      -38.195656 144.304955
Processing Feedback ...