The Resource Routing congestion in VLSI circuits : estimation and optimization, Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar

Routing congestion in VLSI circuits : estimation and optimization, Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar

Label
Routing congestion in VLSI circuits : estimation and optimization
Title
Routing congestion in VLSI circuits
Title remainder
estimation and optimization
Statement of responsibility
Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
Creator
Contributor
Subject
Language
eng
Cataloging source
UKM
Dewey number
621.395
Illustrations
illustrations
Index
index present
LC call number
TK7874.75
LC item number
.S39 2007
Literary form
non fiction
Nature of contents
bibliography
Series statement
Series on integrated circuits and systems
Label
Routing congestion in VLSI circuits : estimation and optimization, Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
Publication
Bibliography note
Includes bibliographical references and index
http://library.link/vocab/branchCode
  • net
Control code
000042129729
Dimensions
24 cm
Extent
xiv, 248 p.
Isbn
9780387300375
Lccn
2006939848
Other physical details
ill.
http://library.link/vocab/recordID
.b23039218
System control number
ebl302208

Library Locations

    • Deakin University Library - Geelong Waurn Ponds CampusBorrow it
      75 Pigdons Road, Waurn Ponds, Victoria, 3216, AU
      -38.195656 144.304955
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